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2 a/1.25 a, 1.2 mhz, synchronous, step - down dc - to - dc regulators data sheet ADP2119/adp2120 rev. a information furnished by analo g devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change wit hout notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 C 2012 analog devices, inc. all rights reserved. features continuous output current ADP2119: 2 a adp2120: 1.25 a 1 4 5 m ? and 7 0 m ? integrated mos fet s input voltage range from 2.3 v to 5.5 v output voltage from 0.6 v to v in 1.5% output accuracy 1.2 mhz fixed switching frequency synchronizable between 1 mhz and 2 mhz selectable pwm or pfm mode operation current mode architecture precision threshold enable input power - good flag voltage tracking integrated soft start internal compensation start up with precharged output uvlo, ovp, ocp, and thermal shutdown 10- lead , 3 mm 3 mm lfcsp _wd package supported by adisimpower ? design tool applications point of load conversion communications and networking equipment industrial and instrumentation consumer electronic s medical application s typical application circuit 10 en ADP2119/adp2120 1 vin 9 sync/mode 2 pvin 8 pgood 3 sw 7 trk 4 pgnd 6 fb 5 gnd r2 10k? v in 5v c in 22f x5r 6.3v c out 22f x5r 6.3v c1 0.1f r1 10? r bot 2.21k? v out 3.3v l 1.5h r top 10k? 08716-001 figure 1. general description the ADP2119/adp2120 are low quiescent current, synchronous, step - down dc - to - dc regulators in a compact 3 mm 3 mm lfcsp _wd package. both devic es use a current mode, constant frequency pulse - width modulation (pwm) control scheme for excellent stability and transient response. under light load condition s , they can be configured to operate in a pulse frequency modulation (pfm) mode , which reduces s witching frequency to save power. the ADP2119 /adp2120 support input voltages from 2.3 v to 5.5 v. the output voltage can be adjusted from 0.6 v up to the input voltage (v in ) for the adjustable version, whe reas the fixed output version is available in prese t output voltage options of 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v , and 1.0 v. the ADP2119/adp2120 require minimal external parts and provide a high efficiency solution with their integrated power switches, synchronous rectifier s , and internal compensation. eac h ic draws less than 2 a current from the input source when it is disabled. o ther key features include underv oltage lockout (uvlo), integrated soft start to limit inrush current at startup, overvoltage protection (ovp), overcurrent protection (ocp) , and t hermal shutdown (tsd). 100 90 80 70 60 50 40 30 20 10 0 0.01 0.1 1 efficiency (%) output current (a) pfm fpwm v in = 5v v out = 1.8v 08716-002 figure 2 . ADP2119 efficiency vs. output current
ADP2119/adp2120 data sheet rev. a | page 2 of 24 table of contents features .............................................................................................. 1 appl ications ....................................................................................... 1 typical application circuit ............................................................. 1 general description ......................................................................... 1 r evision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 th ermal resistance ...................................................................... 5 boundary condition .................................................................... 5 esd caution .................................................................................. 5 pin config uration and function descriptions ............................. 6 typical performance characteristics ............................................. 7 functional block diagram ............................................................ 15 theory of operation ...................................................................... 16 control scheme .......................................................................... 16 pwm mode operation .............................................................. 16 pfm mode operation ................................................................ 16 slope compensation .................................................................. 16 enable/shutdown ....................................................................... 16 integrated soft start ................................................................... 16 tracking ....................................................................................... 17 oscillator and synchronization ................................................ 17 current limit and short - circuit protection .............................. 17 overvoltage protection (ovp) ................................................. 17 undervo ltage lockout (uvlo) ............................................... 17 thermal shutdown .................................................................... 17 power good (pgood) ............................................................. 17 applications information .............................................................. 18 adisimpower design tool ....................................................... 18 output voltage selection ........................................................... 18 inductor selection ...................................................................... 18 output capacitor selection ....................................................... 18 input capacitor selection .......................................................... 19 voltage tracking ......................................................................... 19 typical application circuits ......................................................... 20 outline dimensions ....................................................................... 22 ordering guide .......................................................................... 22 revision history 8 /1 2 rev. 0 to rev. a change to features section ............................................................. 1 added adisimpower design tool section ................................. 1 8 updated outline dimensions ....................................................... 22 changes to orderi ng guide .......................................................... 22 6 / 10 rev ision 0: initial version
data sheet ADP2119/adp212 0 rev. a | page 3 of 24 specifications v in = v pvin = 3 .3 v, en = vin, sync/mode = vin at t j = ?40c to +125c, unless otherwise noted . table 1 . parameter symbol test conditions/comments min typ max unit vin and pvin vin voltage range v in 2.3 5.5 v pvin voltage range v pvin 2.3 5.5 v quiescent current i vin no switching, sync/mode = gnd 150 200 a switching, no load, sync/mode = vin 680 900 a shutdown current i shdn v in = v pvin = 5.5 v, en = gnd 0.3 2 a vin undervoltage lockout threshold uvlo v in rising 2.2 2.3 v v in falling 2 2.1 v output char acteristics load regulation 1 ADP2119, i o = 0 a to 2 a 0.08 %/a load regulation 2 adp2120, i o = 0 a to 1.25 a 0.08 %/a line regulation 1 ADP2119, i o = 1 a 0.05 %/v line regulation 2 adp2120, i o = 1 a 0.05 %/v fb fb regulation voltage v fb v in = 2.3 v to 5.5 v 0.591 0.6 0.609 v fb bias current i fb v in = 2.3 v to 5.5 v 0.01 0.1 a sw high - side on resistance 3 v in = v pvin = 3.3 v, i sw = 200 ma 1 45 190 m? low - side on resistance 3 v in = v pvin = 3.3 v, i sw = 200 ma 7 0 100 m? sw peak current limit high - side switch, v in = v pvin = 3.3 v (ADP2119) 2. 5 3 3. 5 a high - side switch, v in = v pvin = 3.3 v (adp2120 ) 1.6 2 2.4 a s w maximum duty cycle v in = v pvin = 5.5 v, full frequency 100 % sw minimum on tim e 4 v in = v pvin = 5.5 v, full frequency 100 ns trk trk input voltage range 0 600 mv trk -to - fb offset voltage trk = 0 mv to 500 mv ? 1 5 +1 5 mv trk input bias current 100 na frequency oscillator frequency f s 1.0 2 1.2 1.3 8 mhz sync/mode synchronization range 1 2 mhz sync minimum pulse width 100 ns sync minimum off time 100 ns sync input high voltage 1.3 v sync input low vo ltage 0.4 v integrated soft start soft start time all switching frequencies 1024 clock cycles f s = 1.2 mhz 853 s pgood power - good range fb rising threshold 105 110 115 % fb rising hysteresis 2.5 % fb falling threshold 85 90 95 % fb falling hysteresis 2.5 % power - good deglitch time from fb to pgood 16 clock cycles pgood leakage current v pgood = 5 v 0.1 1 a pgood output low voltage i pgood = 1 ma 150 200 mv pgood output low resistor i pgood = 1 ma 150 200 ?
ADP2119/adp2120 data sheet rev. a | page 4 of 24 parameter symbol test conditions/comments min typ max unit en en input rising threshold v in = 2.3 v to 5.5 v 1.12 1.2 1.28 v en input hysteresis v in = 2.3 v to 5.5 v 100 mv en pull - down resistor 1 m? thermal thermal shutdown threshold 150 c thermal shutdown hysteresis 25 c 1 specified by the circuit in figure 54. 2 specified by the circuit in figure 58. 3 pin - to - pin measurements. 4 guaranteed by design.
data sheet ADP2119/adp212 0 rev. a | page 5 of 24 absolute maximum rat ings table 2 . parameter rating vin, pvin ? 0.3 v to +6 v sw ? 0.3 v to +6 v fb, sync/mode, en, trk, pgood ? 0.3 v to +6 v pgnd to gnd ? 0.3 v to +0.3 v operating junction temperature range ? 40c to +125c storage temperature range ? 65c to +150c soldering conditions jedec j - std -020 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at thes e or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for th e worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja unit 10- lead lfcsp_wd 40 c /w boundary condition ja is measured using natural convect ion on a jedec 4 - layer board, and the exposed pad is soldered to the printed circuit board (pcb) with thermal vias. esd caution
ADP2119/adp2120 data sheet rev. a | page 6 of 24 pin configuration an d function descripti ons 10 en ADP2119/adp2120 exposed pad 1 vin 9 sync/mode 2 pvin 8 pgood 3 sw 7 trk 4 pgnd 6 fb 5 gnd notes 1. the exposed pad should be soldered to an external ground plane underneath the ic for thermal dissipation. 08716-003 figure 3. pin configuration (top view) table 4 . pin function descriptions pin o. nemonic description 1 vin bias voltage input pin. connect a bypass capacitor (0.1 f minimum ) between this pin and gnd and a small (10 ?) resistor between this pin and pvin. 2 pvin power input pin . connect this pin to the input power source. connect a bypass capacitor between this pin and pgnd. 3 sw switch node output. connect this pin to the output inductor. 4 pgnd power gr ound. connect this pin to the power ground plane and to the high current return for the power mosfet. 5 gnd analog ground. connect this pin to the ground plane. 6 fb feedback voltage sense input. connect this pin to a resistor divider from v o ut . for the fixed output version, connect to v o ut directly. 7 trk tracking input. to track a master voltage, drive trk from a resistor divider from the master voltage. if the tracking function is not used, connect trk to vin. 8 pgood power - good output (open drain). connect this pin to a resistor to any pull - up voltage < 5.5 v. 9 sync/mode synchronization input (sync). connect this pin to an external clock between 1 mhz and 2 mhz to synchronize the switching frequency to the external clock (see the oscillator and synchronization section for details). fpwm/pfm selection (mode). when this pin is connected to vin, the pfm mode is disabled and the part works in continuous conduction mode (ccm) only . when this pin is connected to ground, the pfm mode is enabled and becomes active at light loads. 10 en precision threshold enable input pin. an external resistor divider can be used to set the turn - on threshold. to enable the part automatically, connect the en pin to vin. this pin has a 1 m? pul l - down resistor to gnd. epad exposed pad the exposed pad should be soldered to an external ground plane underneath the ic for thermal dissipation.
data sheet ADP2119/adp212 0 rev. a | page 7 of 24 typical performance characteristics t a = 25c, v in = v pvin = 5 v, v out = 1.2 v, l = 1.5 h, c in = 22 f, c out = 2 22 f, unless otherwise noted. 100 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v inductor sumida cdrh5d18bhpnp-1r5m 08716-004 figure 4 . efficiency (ADP2119, v in = 3.3 v, fpwm) vs. output current 100 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v inductor sumida cdrh5d18bhpnp-1r5m 08716-005 figure 5 . efficiency (ADP2119, v in = 5 v, fpwm) vs. output current 100 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v inductor sumida cdrh5d18bhpnp-1r5m 08716-006 figure 6 . efficiency (adp2120, v in = 3.3 v, fpwm) vs. output current 100 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v inductor sumida cdrh5d18bhpnp-1r5m 08716-007 figure 7 . efficiency (ADP2119, v in = 3.3 v, pfm) vs. output current 100 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v inductor sumida cdrh5d18bhpnp-1r5m 08716-008 figure 8 . efficiency (ADP2119, v in = 5 v, pfm) v s. output current 100 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v inductor sumida cdrh5d18bhpnp-1r5m 08716-009 figure 9 . efficiency (adp2120, v in = 3.3 v, pfm) vs. output current
ADP2119/adp2120 data sheet rev. a | page 8 of 24 100 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v inductor sumida cdrh5d18bhpnp-1r5m 08716-010 figure 10 . efficiency (adp2120, v in = 5 v, fpwm) vs. output current 900 850 800 750 700 650 600 550 500 450 400 2.3 5.5 5.1 4.7 4.3 3.9 3.5 3.1 2.7 quiescent current (a) v in (v) t j = +125c t j = +25c t j = ?40c 08716-011 figure 11 . q uiescent current vs. v in ( switching) 275 250 225 200 175 150 125 100 75 50 2.3 5.5 5.1 4.7 4.3 3.9 3.5 3.1 2.7 pfet resistor (m?) v in (v) t j = +125c t j = +25c t j = ?40c 08716-012 figure 12 . pfet resistor vs. v in (pin - to - pin measurements) 100 0 10 20 30 40 50 60 70 80 90 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 efficiency (%) output current (a) v out = 1.0v v out = 1.2v v out = 1.5v v out = 1.8v v out = 2.5v v out = 3.3v inductor sumida cdrh5d18bhpnp-1r5m 08716-013 figure 13 . efficiency (adp2120, v in = 5 v, pfm) vs. output current 605 604 603 602 601 600 599 598 597 596 595 594 ?40 120 100 80 60 40 20 0 ?20 feedback voltage (mv) temperature (c) 08716-014 figure 14 . feedback voltage vs. temperature (v in = 3.3 v) 120 110 100 90 80 70 60 50 40 30 2.3 5.5 5.1 4.7 4.3 3.9 3.5 3.1 2.7 nfet resistor (m?) v in (v) t j = +125c t j = +25c t j = ?40c 08716-015 figure 15 . nfet resistor vs. v in (pin - to- pin measurements)
data sheet ADP2119/adp212 0 rev. a | page 9 of 24 1.30 1.00 1.05 1.10 1.15 1.20 1.25 ?40 120 100 80 60 40 20 0 ?20 en threshold (v) temperature (c) falling rising 08716-016 figure 16 . en threshold vs. temperature 3.1 2.5 2.6 2.7 2.8 2.9 3.0 ?40 120 100 80 60 40 20 0 ?20 peak current limit (a) temperature (c) 08716-017 figure 17 . p eak current limit vs. temperature (ADP2119, v in = 3.3 v) 2.10 2.05 1.75 1.80 1.85 1.90 1.95 2.00 ?40 120 100 80 60 40 20 0 ?20 peak current limit (a) temperature (c) 08716-018 figure 18 . peak current limit vs. temperature (adp2120, v in = 3.3 v) 2.30 2.00 2.05 2.10 2.15 2.20 2.25 ?40 120 100 80 60 40 20 0 ?20 uvlo threshold (v) temperature (c) falling rising 08716-019 figure 19 . uvlo threshold vs. temperature (v in = 3.3 v) 3.5 3.3 3.1 2.9 2.7 2.5 2.3 2.1 2.3 5.5 5.1 4.7 4.3 3.9 3.5 3.1 2.7 peak current limit (a) v in (v) t j = +125c t j = +25c t j = ?40c 08716-020 figure 20 . peak current limit vs. v in (ADP2119 ) 2.2 2.1 2.0 1.9 1.8 1.7 1.6 2.3 5.5 5.1 4.7 4.3 3.9 3.5 3.1 2.7 peak current limit (a) v in (v) t j = +125c t j = +25c t j = ?40c 08716-021 figure 21 . peak current limit vs. v in (adp2120 )
ADP2119/adp2120 data sheet rev. a | page 10 of 24 ch1 500mv ch2 5.00v ch3 5.00v ch4 2.00a ? m400s a ch3 3.60v t 30.4% 3 1 2 4 t en v out pgood i l 08716-022 figure 22 . soft start with full load (ADP2119, v in = 5 v) ch1 50.0mv ch4 1.00a ? m200s a ch4 880ma t 596.0s 1 4 t v out (ac) i o 08716-023 figure 23 . load transient (ADP2119, pfm, v in = 5 v) ch1 50.0mv ch4 1.00a ? m200s a ch4 960ma t 396.0s 1 4 t v out (ac) i o 08716-024 figure 24 . load transient (adp2120, pfm, v in = 5 v) ch1 500mv ch2 5.00v ch3 5.00v ch4 2.00a ? m400s a ch3 3.50v t 784.0s 3 1 2 4 t en v out pgood i l 08716-025 figure 25 . soft start with precharge d output (ADP2119, v in = 5 v) ch1 50.0mv ch4 1.00a ? m200s a ch4 880ma t 596.0s 1 4 t v out (ac) i o 08716-026 figure 26 . load transient (ADP2119, fpwm, v in = 5 v) ch1 50.0mv ch4 1.00a ? m200s a ch4 960ma t 396.0s 1 4 t v out (ac) i o 08716-027 figure 27 . load transient (adp2120, fpwm, v in = 5 v)
data sheet ADP2119/adp212 0 rev. a | page 11 of 24 ch1 500mv ch2 5.00v ch4 2.00a ? m2.0ms a ch1 480mv t 3.92ms 1 2 4 t v out sw i l 08716-028 figure 28 . output short (ADP2119) ch1 500mv ch2 5.00v ch4 2.00a ? m2.0ms a ch1 200mv t 3.96ms 1 2 4 t v out sw i l 08716-029 figure 29 . output short (adp2120) ch1 500mv ch2 500mv m2.0ms a ch2 730mv t 44.4% 1 t trk fb 08716-030 figure 30 . tracking function ch1 500mv ch2 5.00v ch4 2.00a ? m2.0ms a ch1 560mv t ?2.08ms 1 2 4 t v out sw i l 08716-031 figure 31 . output short recovery (ADP2119) ch1 500mv ch2 5.00v ch4 2.00a ? m2.0ms a ch1 560mv t ?2.12ms 1 2 4 t v out sw i l 08716-032 figure 32 . output short recovery (adp2120) ch1 2.0v ch2 2.0v m400ns a ch1 4.12v t 0.0s 1 2 sync sw t 08716-033 figure 33 . synchronized to 1 mhz
ADP2119/adp2120 data sheet rev. a | page 12 of 24 ch1 20.0mv ch2 5.00v ch4 500ma ? m4.0s a ch4 820ma t ?40.0ns 1 2 4 t v out (ac) sw i l 08716-034 figure 34 . pfm mode ch1 5.0mv ch2 5.00v ch4 500ma ? m1.0s a ch2 4.3v t ?40.0ns 1 2 4 t v out (ac) sw i l 08716-035 figure 35 . discontinuous conduction mode (d cm) ch1 5.0mv ch2 5.00v ch4 1.0a ? m1.0s a ch2 4.3v t ?40.0ns 1 2 4 t v out (ac) sw i l 08716-036 figure 36 . continuous conduction mode (c cm) 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 124khz phase margin: 46 08716-037 figure 37 . ADP2119 bode plot at v in = 5 v, v out = 1.0 v, i o = 2 a , l = 1 h, c out = 2 22 f 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 105khz phase margin: 47 08716-038 figure 38 . ADP2119 bode plot at v in = 5 v, v out = 1.2 v , i o = 2 a, l = 1.5 h, c out = 2 22 f 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 112khz phase margin: 48 08716-039 figure 39 . ADP2119 bode plot at v in = 5 v, v out = 1.5 v , i o = 2 a, l = 1.5 h, c out = 22 f + 10 f
data sheet ADP2119/adp212 0 rev. a | page 13 of 24 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 99khz phase margin: 52 08716-040 figure 40 . ADP2119 bode plot at v in = 5 v, v out = 1.8 v , i o = 2 a, l = 1.5 h, c out = 22 f + 10 f 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 107khz phase margin: 49 08716-041 figure 41 . ADP2119 bode plot at v in = 5 v, v out = 2.5 v , i o = 2 a, l = 1.5 h, c out = 22 f 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 89khz phase margin: 58 08716-042 figure 42 . ADP2119 bode plot at v in = 5 v, v out = 3.3 v , i o = 2 a, l = 1.5 h, c out = 22 f 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 87khz phase margin: 48 08716-043 figure 43 . adp212 0 bode plot at v in = 5 v, v out = 1.0 v, i o = 1.25 a , l = 1.5 h, c out = 22 f + 10 f 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 80khz phase margin: 54 08716-044 figure 44 . adp2120 bode plot at v in = 5 v, v out = 1.2 v , i o = 1.25 a , l = 1.5 h, c out = 22 f + 10 f 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 67khz phase margin: 51 08716-045 figure 45 . adp2120 bode plot at v in = 5 v, v out = 1.5 v , i o = 1.25 a , l = 2.2 h, c out = 22 f + 10 f
ADP2119/adp2120 data sheet rev. a | page 14 of 24 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 78khz phase margin: 50 08716-046 figure 46 . adp2120 bode plot at v in = 5 v, v out = 1.8 v , i o = 1.25 a , l = 2.2 h, c out = 2 10 f 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 61khz phase margin: 54 08716-047 figure 47 . adp2120 bode plot at v in = 5 v, v out = 2.5 v , i o = 1.25 a , l = 2.2 h, c out = 2 10 f 80 ?80 ?64 ?48 ?32 ?16 0 16 32 48 64 200 ?200 ?160 ?120 ?80 ?40 0 40 80 120 160 1k 10k 100k 1m magnitude (db) phase (degrees) frequency (hz) cross frequency: 48khz phase margin: 60 08716-048 figure 48 . adp2120 bode plot at v in = 5 v, v out = 3.3 v , i o = 1.25 a , l = 2.2 h, c out = 2 10 f
data sheet ADP2119/adp212 0 rev. a | page 15 of 24 functional block dia gram nmos current sense amplifier zero-crossing comparator pgnd pvin pmos current sense amplifier 0.6v error amplifier 0.54v fb slope compensation oscillator skip mode threshold skip comparator sync/mode pwm and protection logic control clk sw en uvlo vin pfet nfet gnd trk z comp 0.66v pgood soft start gm ADP2119/ adp2120 08716-049 fig ure 49 . functional block diagram
ADP2119/adp2120 data sheet rev. a | page 16 of 24 theory of operation the ADP2119/ adp2120 are step - down, dc - to - dc regulators that use a fixed frequency, peak current mode architecture with integrate d high - side switch and low - side synchronous rect ifier. the high switching frequency and tiny 10 - lead, 3 mm 3 mm lfcsp_wd package provide a small step - down dc - to - dc regulator solution. the integrated high - side switch (p - channel mosfet) and synchronous rectifier (n - channel mosfet) yield high efficiency at medium - to - full loads while light load efficiency is improved using the pfm mode. the ADP2119/adp2120 support i nput voltage s from 2.3 v to 5.5 v and regulate the output voltage down to 0.6 v. t h e ADP2119/adp2120 are also available with preset output v oltage options of 3.3 v, 2.5 v, 1.8 v, 1.5 v, 1.2 v , and 1.0 v. control scheme t he ADP2119/adp2120 use a fixed frequency, peak current mode pwm control architecture and operate in pwm mode for medium - to - full loads but shift to pfm mode (if enabled) at lig ht loads to maintain high efficiency. when operating in fixed frequency pwm mode, the duty cycle of the integrated switches is adjusted to regulate the output voltage. when operating in pfm mode at light loads, the switching frequency is adjusted to regul ate the output voltage. the ADP2119/adp2120 operate in pwm mode when the load current is greater than the pulse - skipping threshold current. at load currents below this value, the regulator smoothly transitions to the pfm mode of operation. pwm mode operat ion in pwm mode, the ADP2119/adp2120 operate at a fixed frequency. at the start of each oscillator cycle, the p - channel mosfet switch is turned on, putting a positive voltage across the inductor. current in the inductor increases until the current sense si gnal crosses the peak inductor current level, turns off the p - channel mosfet switch, and turns on the n - channel mosfet synchronous rectifier. this puts a negative voltage across the inductor, causing the inductor current to decrease. the synchronous rectif ier stays on for the rest of the cycle or until the inductor current reaches zero, which causes the zero - crossing comparator to turn off the n - channel mosfet as well. the peak inductor current level is set by v comp . v comp is the output of a transconductan ce error amplifier that compares the feedback voltage with an internal 0.6 v reference. pfm mode operation when pfm mode is enabled, the regulator smoothly transitions to the variable frequency pfm mode of operation when the load current decreases b elow the p ulse - skipping threshold current. s witching continues only as necessary to maintain the output voltage within regulation. when the output voltage drops below regulation, the part enters pwm mode for a few oscillator cycles to increase the output v oltage back to regulation. during the wait time between bursts, both power switches are off, and the output capacitor supplies the load current. because the output voltage dips and recovers occasionally, the output voltage ripple in this mode is larger tha n the ripple in the pwm mode of operation. slope compensation slope compensation stabilizes the internal current control loop of the ADP2119/adp2120 when operating close to and beyond the 50% duty cycle to prevent subhar monic oscillations. slope compensati on is imple mented by summing an artificial voltage ramp to the current sense signal during the on - time of the p - channel mosfet switch. this voltage ramp depends on the output voltage . when operating at high output voltages, there is more slope compensation . the slope compensation ramp value determines the minimum inductor that can be used to prevent subharmonic oscillations. enable/shutdown the en input pin has a precision analog threshold of 1.2 v (typical) with 100 mv of hysteresis. w hen the enable voltag e exceeds 1.2 v, the regulator turns on, and when it falls below 1.1 v (typical ) , the regulator turns off. to force the part to automatically start when input power is applied, connect en to vin. when the ADP2119/adp2120 are shut down, the soft start capa citor is discharged. this causes a new soft start cycle to begin when the part is reenabled. an internal pull - down resistor (1 m?) prevents an accidental enable if en is left floating. integrated soft star t the ADP2119/adp2120 include integrated soft star t circuitry to limit the output voltage rise time and reduce inrush current at startup. the soft start time is fixed at 1024 clock cycles. if the output voltage is precharged prior to turn - on, the part prevents reverse inductor current ( which would dischar ge the output capacitor) by keeping both mosfets turn ed off until the soft start voltage exceeds the voltage on the fb pin.
data sheet ADP2119/adp212 0 rev. a | page 17 of 24 t racking the ADP2119/adp2120 have a tracking input, trk, that allow s the output voltage to track another voltage (master voltag e). the tracking input is especially useful in core and i/o voltage tracking for fpgas, dsps, and asics. the internal error amplifier includes three positive inputs : the internal reference voltage, the soft start voltage , and the trk voltage. the error amp lifier regulates the fb voltage to the lowest of the three voltage s . to track a master voltage, tie the trk pin to a resistor divider from the master voltage. if the tracking function is not used, connect the trk pin to vin. oscillator and synch ronization to synchronize the ADP2119/adp2120, drive an external clock at the sync/mode pin. the frequency of the external clock can be in the 1 mhz to 2 mhz range. during synchronization, the regulator operates in ccm mode only , and the switching frequency is in pha se with the external clock . current limit and sh ort - circuit protection the ADP2119/adp2120 have a peak current limit protection circ uit to prevent current runaway. when the inductor peak current reaches the current limit value, the high - side mos fet turns o ff and the low - side mos fet turns on until the next cycle starts. the overcurrent counter increments during this time. if the overcurrent counter count exceeds 10, the part enters hiccup mode and both t he high - side mos fet an d low - side mos fet are turned off. the part remains in this mode for 4096 clock cycles and then attempts to restart from soft start. if the current limit fault has cleared, the part resumes normal operation. otherwise, it reenters hiccup mode again after counting 10 current limit violatio ns. overvoltage protecti on (ovp) the output voltage is continuously monitored by a comparator through the fb pin, which is at 0.6 v (typical) under normal operation. this comparator is set to activate when the fb voltage exceeds 0.66 v (typical), thu s indicating an output overvoltage condition. if the voltage remains above this threshold for 16 clock cycles, the high - side mosfet turns off and the low - side mosfet turns on until the current through the low - side mosfet reaches the limit ( ? 0.6 a for forced continuous conduction mode and 0 a for pfm mode). thereafter, both the mosfets are held in the off state until fb falls below 0.54 v (typical), at this point , the part restart s . the behavior of pgood under this condition is described in t he power good section. undervoltage lockout (uvlo) undervoltage lockout circuitry is integrated in the ADP2119/ adp2120. if the input voltage drops below 2.1 v, the part shuts down and both the power switch and synchronous rectifi er turn off. when the voltage rises again above 2.2 v, the soft start period is initiated , and the part is enabled. thermal shutdown if the ADP2119/adp2120 junction temperatures rise above 150 c, the thermal shutdown circuit turns off the regulators . extre me junction temperatures can be the result of high current operation, poor circuit board design, and/or high ambient temperature. a 25 c hysteresis is included so tha t if thermal shutdown occurs, the part does not return to operation until the on - chip temp erature drops below 125 c. when coming out of thermal shutdown, soft start is initiated. power good (pgood) pgood is an active high, open - drain output and requires a resistor to pull it up to a voltage. a high indicates that the voltage on the fb pin (and therefore the output voltage) is within 10% of the desired value. a low on this pin indicates that the voltage on the fb pin is not within 10% of the desired value. there is a 16 cycle waiting period after fb is detected as being out of bounds.
ADP2119/adp2120 data sheet rev. a | page 18 of 24 applic ations information adi sim p ower design tool the ADP2119/adp2120 are supported by adisimpower design tool set. adisimpower is a collection of tools that pr oduce complete power designs optimized for a specific design goal. the tools enable the user to generate a full schematic, bill of materials, and calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and parts count while taking into consideration the operating conditions and limitations of the ic and all real external components. for more information about adisimpow er design tools, refer to www.analog.com/adisimpower . the tool set is available from this website, and users can also request an unpopulated board through the tool. t h is section describes the selection o f th e external components for the ADP2119/adp2120 . the typical application circuit for the ADP2119 is shown in figure 50. 10 en ADP2119 1 vin 9 sync/mode 2 pvin 8 pgood 3 sw 7 trk 4 pgnd 6 fb 5 gnd r2 10k? v in 5v c in 22f x5r 6.3v c out 22f x5r 6.3v c1 0.1f r1 10? r bot 15k? v out 2.5v 2a l 1.5h r top 47.5k? 08716-050 figure 50 . typical application circuit output voltage selec tion the output voltage of the adjustable version can be set by an external resistive voltage divider , and the following equation calculates the output voltage . ) (1 0.6 bot top out r r v + = to lim it the output voltage accuracy degradation due to fb bias current (0.1 a maximum) to less than 0.5% (maximum), ensure that r bot is less than 30 k?. inductor selection the inductor value is determined by the operating frequency, input voltage, output voltage , and ripple current. a small inductor value leads to a larger inductor current ripple and provides a fast er transient respons e ; however, it degrades efficiency. a large inductor value leads to a smaller current ripple and good efficiency but slow s the transient response. as a guideline, the inductor current ripple , i l , is typically set to 1/3 of the maximum load current trade - o ff between the transient response and efficiency. the inductor value can be calculated using the following equation: ( ) s l out in f i d v v l ? = where: v in is the input voltage. v out is the output voltage. i l is the inductor current ripple. d is the duty cycle . d = v out / v in . the regulator uses slope compensation in the current loop to prevent subharmonic oscillations when the duty cycle is larger than 50%. the internal slope compensation limits the minimum inductor value. the negative current limit (?0.6 a) als o limits the minimum inductor value. the inductor current ripple ( i l ) calculated by the selected inductor should not exceed 1.2 a. the peak inductor current should be kept below the peak current limit threshold value and can be calculated from 2 l o peak i i i ? + = ensure that the rms current of the selected inductor is greater than the maximum load current and that its saturation current is greater than the p eak current limit of the regulato r. output capacitor sel ection the output voltage ripple, load step transient, and loop stability determine the output capacitor selection. the esr and the capacitance determine t he output ripple. ? ? ? ? ? ? ? ? + ? = ? s out l out f c esr i v 8 1 the load transient response depends on the inductor, the output capacitor, and the control loop. the ADP2119/adp2120 have integrated loop compensation to provide a simple power solution design. table 5 and table 6 show the typical recommended inductors and capacitors f or the ADP2119/ adp2120. x5r or x7r ceramic capacitors are highly recommended. table 5 . recommended l and c out value s for the ADP2119 v in (v) v o ut (v) l (h) c out (f) 3.3 1.0 1 22 + 22 3.3 1.2 1 22 + 22 3.3 1.5 1 22 + 10 3.3 1 .8 1 22 3.3 2.5 1 22 5 1.0 1 22 + 22 5 1.2 1.5 22 + 22 5 1.5 1.5 22 +10 5 1.8 1.5 22 +10 5 2.5 1.5 22 5 3.3 1.5 22
data sheet ADP2119/adp212 0 rev. a | page 19 of 24 table 6 . recommended l and c out value s for the adp2120 v in (v) v o ut (v) l (h) c out (f) 3.3 1.0 1.5 22 + 10 3.3 1.2 1.5 22 + 10 3.3 1.5 1.5 22 + 10 3.3 1.8 1.5 10 + 10 3.3 2.5 1.5 10 + 10 5 1.0 1.5 22 + 10 5 1.2 1.5 22 + 10 5 1.5 2.2 22 + 10 5 1.8 2.2 10 + 10 5 2.5 2.2 10 + 10 5 3.3 2.2 10 + 10 higher or lower inductor and output capacitor valu es can be used in the regulator, but the system stability and load transient performance need to be checked. the minimum output capacitor is 22 f for the ADP2119 and 10 f for the adp2120, and t he inductor range is 1 h to 3.3 h. table 7 . recommended inductors manufacturer part number sumida cdrh5d18bhpnp, cdr6d23mnnp toko de4518c, d62lcb coilcraft lps5030, lps5015 table 8 . recommended capacitors manufacturer part number description murata grm31cr60j22 6ke19 22 f, 6.3 v, x5r, 1206 murata grm319r60j106ke19 10 f, 6.3 v, x5r, 1206 tdk c3216x5r0j226m 22 f, 6.3 v, x5r, 1206 tdk c3216x5r0j106m 10 f, 6.3 v, x5r, 1206 input capacitor sele ction the input capacitor reduces the input voltage ripple caused b y the switch current on pvin. place the input capacitor as close as possible to the pvin pin. a 10 f or 22 f ceramic capacitor is recommended. the rms current rating of the input capacitor should be larger than calculated by the fol lowing equation: ) 1 ( d d i i o rms ? = voltage tracking the ADP2119/adp2120 include a tracking feature that allows the output (slave voltage) to be configured to track an external voltage (master voltage), as shown in figure 51. ADP2119/ adp2120 trk fb v master r trkb r trkt r bot r top v slave 08716-051 figure 51 . voltage tracking a common application is coincident tracking ( see figure 52) . coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. connect the t rk pin to a resistor divider from the master voltage. for coincident tracking, set r trkt = r top and r trkb = r bot . voltage time v master v slave 08716-052 figure 52 . coincident tracking ratiometric tracking is shown in figure 53 . the slave outp ut is limited to a fraction of the master voltage. in this application, the slave and master voltages reach the final value at the same time. the ratio of the slave output voltage to the master voltage is a function of the two dividers (see the following e quation) . trkb trkt bot top master slave r r r r v v + + = 1 1 voltage time v master v slave 08716-053 figure 53 . ratiometric tracking
ADP2119/adp2120 data sheet rev. a | page 20 of 24 typical application circuits 10 en ADP2119 1 vin 9 sync/mode 2 pvin 8 pgood 3 sw 7 trk 4 pgnd 6 fb 5 gnd r2 10k? v in 5v c in 22f x5r 6.3v c out2 22f x5r 6.3v c out1 22f x5r 6.3v c1 0.1f r1 10? r bot 10k? v out 1.2v 2a l 1.5h r top 10k? l: cdrh5d18bhpnp-1r5m sumida c in , c out1 , c out2 : grm31cr60j226ke19 murata 08716-054 figure 54 . 1.2 v, 2 a, step - down regulator, force d continuous conduction mode (ADP2119) 10 en ADP2119 1 vin 9 sync/mode 2 pvin 8 pgood 3 sw 7 trk 4 pgnd 6 fb 5 gnd r2 10k? v in 5v c in 22f x5r 6.3v c out2 22f x5r 6.3v c out1 10f x5r 6.3v c1 0.1f r1 10? r bot 10k? v out 1.8v 2a l 1.5h r top 20k? l: cdrh5d18bhpnp-1r5m sumida c in , c out2 : grm31cr60j226ke19 murata c out1 : grm319r60j106ke19 murata 08716-055 figure 55 . 1.8 v, 2 a, step - down regulator, enable pfm mode (ADP2119)
data sheet ADP2119/adp212 0 rev. a | page 21 of 24 10 en ADP2119 1 vin 9 sync/mode 2 pvin 8 pgood 3 sw 7 trk 4 pgnd 6 fb 5 gnd r2 10k? v in 5v external clock c in 22f x5r 6.3v c out 22f x5r 6.3v c1 0.1f r1 10? r bot 15k? v out 2.5v 2a l 1.5h r top 47.5k? l: cdrh5d18bhpnp-1r5m sumida c in , c out : grm31cr60j226ke19 murata 08716-056 figure 56 . 2.5 v, 2 a, st ep - down regulator, synchronized to external clock (ADP2119) 10 en adp2120 1 vin 9 sync/mode 2 pvin 8 pgood 3 sw 7 trk 4 pgnd 6 fb 5 gnd r2 10k? v in 5v c in 22f x5r 6.3v c out2 10f x5r 6.3v c out1 22f x5r 6.3v c1 0.1f r1 10? r bot 10k? r trkb 10k? r trkt 15k? v out 1.5v 1.25a l 2.2h r top 15k? l: lps5030-222mlb coilcraft c in , c out1 : grm31cr60j226ke19 murata c out2 : grm319r60j106ke19 murata v master 08716-057 figure 57 . 1.5 v, 1.25 a, step - d own regulator, tracking mode (adp2120) 10 en adp2120 1 vin 9 sync/mode 2 pvin 8 pgood 3 sw 7 trk 4 pgnd 6 fb 5 gnd r2 10k? v in 5v c in 22f x5r 6.3v c out2 10f x5r 6.3v c out1 22f x5r 6.3v c1 0.1f r1 10? r bot 10k? v out 1.2v 1.25a l 1.5h r top 10k? l: cdrh5d18bhpnp-1r5m sumida c in , c out1 : grm31cr60j226ke19 murata c out2 : grm319r60j106ke19 murata 08716-058 figure 58 . 1.2 v, 1.25 a, step - down regulator, force d continuous conduction mode (adp2120)
ADP2119/adp2120 data sheet rev. a | page 22 of 24 outline dimensions 2.48 2.38 2.23 0.50 0.40 0.30 t op view 10 1 6 5 0.30 0.25 0.20 bottom view pin 1 index are a sea ting plane 0.80 0.75 0.70 1.74 1.64 1.49 0.20 ref 0.05 max 0.02 nom 0.50 bsc exposed pa d 3.10 3.00 sq 2.90 pin 1 indic a t or (r 0.15) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. coplanarity 0.08 02-27-2012-b figure 59 . 10 - lead lead frame chip scale package [l fcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp - 10 - 9) dimensions shown in millimeters ordering guide model 1 output current temperature range output voltage package description package option branding ADP2119acpz -r7 2 a ? 40c to +125c adj 10- lead lfcsp_wd cp -10-9 lfl ADP2119acpz - 1.0-r7 2 a ? 40c to +125c 1.0 v 10- lead lfcsp_wd cp -10-9 lev ADP2119acpz - 1.2-r7 2 a ? 40c to +125c 1.2 v 10- lead lfcsp_wd cp -10-9 lfk ADP2119acpz - 1.5-r7 2 a ? 40c to +125c 1.5 v 10- lead lfc sp_wd cp -10-9 lfm ADP2119acpz - 1.8-r7 2 a ? 40c to +125c 1.8 v 10- lead lfcsp_wd cp -10-9 lfn ADP2119acpz - 2.5-r7 2 a ? 40c to +125c 2.5 v 10- lead lfcsp_wd cp -10-9 lfp ADP2119acpz - 3.3-r7 2 a ? 40c to +125c 3.3 v 10- lead lfcsp_wd cp -10-9 lfr adp2120acpz -r7 1.25 a ? 40c to +125c adj 10- lead lfcsp_wd cp -10-9 lew adp2120acpz - 1.0-r7 1.25 a ? 40c to +125c 1.0 v 10- lead lfcsp_wd cp -10-9 lfs adp2120acpz - 1.2-r7 1.25 a ? 40c to +125c 1.2 v 10- lead lfcsp_wd cp -10-9 lft adp2120acpz - 1.5-r7 1.25 a ? 40c to +125 c 1.5 v 10- lead lfcsp_wd cp -10-9 lfu adp2120acpz - 1.8-r7 1.25 a ? 40c to +125c 1.8 v 10- lead lfcsp_wd cp -10-9 lfv adp2120acpz - 2.5-r7 1.25 a ? 40c to +125c 2.5 v 10- lead lfcsp_wd cp -10-9 lfw adp2120acpz - 3.3-r7 1.25 a ? 40c to +125c 3.3 v 10- lead lfcsp_ wd cp -10-9 lfx ADP2119 - evalz evaluation board adp2120 - evalz evaluation board 1 z = rohs compliant part.
data sheet ADP2119/adp212 0 rev. a | page 23 of 24 notes
ADP2119/adp2120 data sheet rev. a | page 24 of 24 notes ? 2010 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are th e property of their respective owners. d08716 - 0- 8/12(a)

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